上機考

module top;

wire A, B, C, D, NA , NB, NC, ND, F1, F2,F3, F4, F5, F ,NF;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nor o1(NA, A, A);
nor o2(NB, B, B);
nor o3(NC, C, C);
nor o4(ND, D, D);

nor o5(F1, A, B, NC, D);
nor o6(F2, NA, NB, NC);
nor o7(F3, NA, B, C);
nor o8(F4, NA, C, D);
nor o9(F5, A, NB, C);
nor o10(NF, F1, F2, F3, F4, F5);
nor o11(F, NF, NF);


endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>800)$stop;

endmodule

12/2 上機考練習

module top;
wire A,B,C,D,F;
system_clock #1600 clock3(A);
system_clock #800 clock5(B);
system_clock #400 clock6(C);
system_clock #200 clock7(D);

not a1(a,A);
not a2(b,B);
not a3(c,C);
not a4(d,D);
and b1(F1,C,D);
and b2(F2,a,b,D);
and b3(F3,B,c,d);
and b4(F4,A,c,d);
or w(F,F1,F2,F3,F4);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>10000)$stop;
endmodule