11/4

module top
  integer ia,ib,is;
  reg  a,b,s;
  wire out;

  mux_structural mux1(out,a,b,s);

initial
begin
for (is=0; is<=1; is = is + 1)
begin
s = is;

for (ia=0; ia<=1; ia = ia+1)
begin
a = ia;
for (ib=0; ib<=1; ib = ib + 1)
begin
b = ib;

#1 $display("a=%d b=%d s=%d   out=%d",a,b,s,out);
end
end
end
end
endmodule

module mux_structural(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;
 not I5 (sel_n, SEL);
 and I6 (sel_a, A, SEL);
 and I7 (sel_b, sel_n, B);
 or I4 (OUT, sel_a, sel_b);
endmodule