module top;

wire A1, B1,SEL,A0,B0 ,OUT1,OUT0;
system_clock #1600 clock1(A1);
system_clock #800 clock2(B1);
system_clock #400 clock3(SEL);
system_clock #200 clock4(A0);
system_clock #100 clock5(B0);

mux S1(OUT1,A1,B1,SEL);
mux S2(OUT0,A0,B0,SEL);